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? freescale semiconductor, inc., 2009-2010. all rights reserved. this document contains information on a new product. specificati ons and information herein are subject to change without notice . 80-lqfp 12mm x 12mm 64-lqfp 10mm x 10mm 81-mapbga 10mm x10mm 8-bit hcs08 central processor unit (cpu) ? up to 48-mhz cpu above 2.4 v, 40 mhz cpu above 2.1 v, and 20 mhz cpu above 1.8 v across temperature of -40c to 105c ? hcs08 instruction set with added bgnd instruction ? support for up to 32 interrupt/reset sources on-chip memory ? 128 k dual array flash read/program/erase over full operating voltage and temperature ? 12 kb random-access memory (ram) ? security circuitry to prevent unauthorized access to ram and flash power-saving modes ? two ultra-low power stop modes. peripheral clock enable register can disable clocks to unused modules to reduce currents ? time of day (tod) ? ultra-low power 1/4 sec counter with up to 64s timeout. ? ultra-low power external oscillator that can be used in stop modes to provide accurate clock source to the tod. 6 usec typical wake up time from stop3 mode clock source options ? oscillator (xosc1) ? loop-control pierce oscillator; 32.768 khz crystal or ceramic resonator dedicated for tod operation. ? oscillator (xosc2) ? for high frequency crystal input for mcg reference to be used for system clock and usb operations. ? multipurpose clock generator (mcg) ? pll and fll; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports cpu frequencies from 4 khz to 48 mhz. system protection ? watchdog computer operating properly (cop) reset watchdog computer operating properly (cop) reset with option to run from dedicated 1-khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points; separate low-voltage warning with optional interrupt; selectable trip points ? illegal opcode and illegal address detection with reset ? flash block protection for each array to prevent accidental write/erasure ? hardware crc to support fast cyclic redundancy checks development support ? single-wire background debug interface ? real-time debug with 6 hardware breakpoints (4 pc, 1 address and 1 data) breakpoint capability to allow single breakpoint setting during in-circuit debugging ? on-chip in-circuit emulator (ice) debug module containing 3 comparators and 9 trigger modes peripherals ? cmt ? carrier modulator timer for remote control communications. carrier generator, modulator and driver for dedicated infrared out. can be used as an output compare timer. ? iic ? up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing ? pracmp ? analog comparator with selectable interrupt; compare option to programmable internal reference voltage; operation in stop3 ? sci ? two serial communications interfaces with optional 13-bit break; option to connect rx input to pracmp output on sci1 and sci2; high current drive on tx on sci1 and sci2; wake-up from stop3 on rx edge ? spi1 ? serial peripheral interface (spi) with 64-bit fifo buffer; 16-bit or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting ? spi2 ? serial peripheral interface with full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting ? tpm ? two 4-channel timer/pwm module; selectable input capture, output compare, or buffered edge- or center-aligned pwm on each channel; external clock input/pulse accumulator ? usb ? supports usb in full-speed device configuration. on-chip transceiver and 3.3v regulator help save system cost, fully compliant with usb specification 2.0. allows control, bulk, interrupt and isochronous transfers. ? adc12 ? 12-bit successive approximation adc with up to 4 dedicated differential channels and 8 single-ended channels; range compare function; 1.7 mv/ c temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6v to 1.8v, configurable hardware trigger for 8 channel select and result registers ? pdb ? programmable delay block with 16-bit counter and modulus and prescale to set reference clock to bus divided by 1 to bus divided by 2048; 8 trigger outputs for adc12 module provides periodic coordination of adc sampling sequence with sequence completion interrupt; back-to-back mode and timed mode ? dac ? 12-bit resolution; 16-word data buffers with configurable watermark . input/output ? up to 47 gpios and 2 output-only pin and 1 input-only pin. ? voltage reference output (vrefo). ? dedicated infrared output pin (iro) with high current sink capability. ? up to 16 kbi pins with selectable polarity. package options ? 81-mbga 10x10 mm ? 80-lqfp 12x12 mm ? 64-lqfp 10x10 mm freescale semiconductor data sheet: advanced information document number: mc9s08je128 rev. 3, 04/2010 mc9s08je128 series covers: mc9s08je128 and mc9s08je64 ? an energy-efficient so lution from freescale non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
? freescale semiconductor, inc., 2009-2010. all rights reserved. this document contains information on a new product. specificati ons and information herein are subject to change without notice . contents related documentation find the most current versio ns of all documents at: http://www.freescale.com. ? reference manual ?mc9s08je128rm contains extensive product information including modes of operation, memory, resets and interrupts, register defin ition, port pins, cpu, and all module information. 1 devices in the mc9s08je128 series.................. 3 2 preliminary electrical characteristics............. 12 2.1 parameter classification ......................................................... 12 2.2 absolute maximum ratings .................................................... 13 2.3 thermal characteristics .......................................................... 14 2.4 electrostatic discharge (esd) prot ection characteristics ...... 15 2.5 dc characteristics .................................................................. 16 2.6 supply current characteristics ............................................... 19 2.7 comparator (pracmp) electricals......................................... 21 2.8 12-bit digital-to-analog converter (dac12lv) electricals ...... 22 2.9 adc characteristics................................................................ 23 2.10 mcg and external oscillator (xosc) characteristics .......... 28 2.11 ac characteristics ................................................................ 31 2.12 spi characteristics ............................................................... 32 2.13 flash specifications .............................................................. 35 2.14 usb electricals ..................................................................... 36 2.15 vref specifications............................................................. 35 3 ordering information......................................... 41 3.1 device numbering system..................................................... 42 3.2 package information............................................................... 42 3.3 mechanical drawings ............................................................. 42 4 revision history ................................................ 43 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 3 1 devices in the mc9s08je128 series the following table summarizes the feature set available in the mc9s08je128 series of mcus. table 1. mc9s08je128 series features by mcu and package feature mc9s08je128 mc9s08je64 pin quantity 81 80 64 64 flash size (bytes) 131072 65535 ram size (bytes) 12k 12k programmable analog comparator (pracmp) yes yes debug module (dbg) yes yes multipurpose clock generator (mcg) yes yes inter-integrated communication (iic) yes yes interrupt request pin (irq) yes yes keyboard interrupt (kbi) 16 16 7 7 port i/o 1 1 port i/o count does not include two (2) output-only and one (1) input-only pins. 47 46 33 33 dedicated analog input pins 12 12 power and ground pins 8 8 time of day (tod) yes yes serial communications (sci1) yes yes serial communications (sci2) yes yes serial peripheral interface 1 (spi1 (fifo)) yes yes serial peripheral interface 2 (spi2) yes yes carrier modulator timer pin (iro) yes yes tpm input clock pin (tpmclk) yes yes tpm1 channels 4 4 tpm2 channels 4 4 2 2 xosc1 yes yes xosc2 yes yes usb yes yes programmable delay block (pdb) yes yes sar adc differential channels 2 2 each differential channel is comprised of 2 pin inputs. 443 3 sar adc single-ended channels 8 8 6 6 voltage reference output pin (vrefo) yes yes non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 4 a complete description of the modules included on each device is provided in the following table. the block diagram in figure 1 shows the structure of th e mc9s08je128 series mcu. table 2. versions of on-chip modules module version analog-to-digital converter (adc12) 1 digital to analog converter (dac) 1 programmable delay block 1 inter-integrated circuit (iic) 3 central processing unit (cpu) 5 on-chip in-circuit debug/emulator (dbg) 3 multi-purpose clock generator (mcg) 3 low power oscillator (xoscvlp) 1 carrier modulator timer (cmt) 1 programable analog comparator (pracmp) 1 serial communications interface (sci) 4 serial peripheral interface (spi) 5 time of day (tod) 1 universal serial bus (usb) 1 timer pulse-width modulator (tpm) 3 system integration module (sim) 1 cyclic redundancy check (crc) 3 keyboard interrupt (kbi) 2 voltage reference (vref) 1 voltage regulator (vreg) 1 interrupt request (irq) 3 flash wrapper 1 gpio 2 port control 1 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 5 figure 1. mc9s08je128 series block diagram non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 6 1.1 pin assignments this section shows the pin assignments for the mc9s08je128 series devices. 1.1.1 64-pin lqfp the following two figures show the 64-pin lqfp pinout configuration. figure 2. 64-pin lqfp pta0/ss1 iro pta5 pta6 ptb0 ptb1/blms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vrefo vss2 ptb2/extal1 ptb3/xtal1 vdd2 ptb4/extal2 ptb5/xtal2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ptd7/rx1 ptd6/tx1 ptd5/scl/tpm1ch3 ptd4/sda/tpm1ch2 ptd3/tpm1ch1 ptd2/tpm1ch0 ptd1/cmpp2/reset ptd0/bkgd/ms ptc7/kbi2p2/clkout/adp11 ptc6/kbi2p1/pracmpo/adp10 ptc5/kbi2p0/cmpp1/adp9 ptc4/kbi1p7/cmpp0/adp8 ptc3/kbi1p6/ss2 /adp7 ptc2/kbi1p5/spsck2/adp6 ptc1/miso2 ptc0/mosi2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ptg0/spsck1 ptf7/miso1 ptf6/mosi1 vdd1 vss1 vbus usb_dp usb_dm vusb33 ptf2/tx2/tpm2ch0 ptf1/rx2/tpm2ch1 pte6/rx2 pte5/tx2 vdd3 vss3 64-lqfp dadp0 dadp3 dadm3 dadm0 daco vrefh nc dadp2 dadm2 nc nc nc nc pta4 pta7 vrefl vssa nc vdda pte4/cmpp3/tpmclk/irq non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 7 1.1.2 80-pin lqfp the following figure shows the 80-pin lqfp pinout configuration. figure 3. 80-pin lqfp pta0/ss1 iro pta1/kbi1p0/tx1 pta2/kbi1p1/rx1/adp4 pta3/kbi1p2/adp5 pta5 pta6 ptb0 ptb1/blms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vrefo vss2 ptb2/extal1 ptb3/xtal1 vdd2 ptb4/extal2 ptb5/xtal2 ptb6/kbi1p3 ptb7/kbi1p4 ptc0/mosi2 pte3/kbi2p6 pte2/kbi2p5 pte1/kbi2p4 pte0/kbi2p3 ptd7/rx1 ptd6/tx1 ptd5/scl/tpm1ch3 ptd4/sda/tpm1ch2 ptd3/tpm1ch1 ptd2/tpm1ch0 ptd1/cmpp2/reset ptd0/bkgd/ms ptc7/kbi2p2/clkout/adp11 ptc6/kbi2p1/pracmpo/adp10 ptc5/kbi2p0/cmpp1/adp9 ptc4/kbi1p7/cmpp0/adp8 ptc3/kbi1p6/ss2 /adp7 ptc2/kbi1p5/spsck2/adp6 ptc1/miso2 ptg0/spsck1 ptf7/miso1 ptf6/mosi1 vdd1 vss1 vbus usb_dp usb_dm vusb33 ptf5/kbi2p7 ptf4/sda ptf3/scl ptf2/tx2/tpm2ch0 ptf1/rx2/tpm2ch1 ptf0/tpm2ch2 pte7/tpm2ch3 pte6/rx2 pte5/tx2 vdd3 vss3 80-lqfp dadp0 dadp1 dadp2 dadp3 dadm3 dadm2 dadm0 dadm1 nc nc nc nc pta4 pta7 vrefl vssa nc daco vrefh nc vdda pte4/cmpp3/tpmclk/irq non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 8 1.1.3 81-pin mapbga the following figure shows the 81-pin mapbga pinout configuration. figure 4. 81-pin mapbga 1234 56789 a iro ptg0 ptf6 usb_dp vbus vusb33 ptf4 ptf3 pte4 b ptf7 pta0 ptg1 usb_dm ptf5 pte7 ptf1 ptf0 pte3 c pta4 pta5 pta6 pta1 ptf2 pte6 pte5 pte2 pte1 d pta7 ptb0 ptb1 pta2 pta3 ptd5 ptd7 pte0 e dadm2 vdd2 vdd3 vdd1 ptd2 ptd3 ptd6 f dadp2 vss2 vss3 vss1 ptb7 ptc7 ptd4 g dadp0 daco dadp3 dadm3 vrefo ptb6 ptc0 ptc1 ptc2 h dadm0 dadm1 dadp1 ptc3 ptc4 ptd0 ptc5 ptc6 j vssa vrefl vrefh vdda ptb2 ptb3 ptd1 ptb4 ptb5 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 9 1.2 pin assignments by packages table 3. package pin assignments package default function alt1 alt2 alt3 composite pin name 81 mapbga 80 lqfp 64 lqfp b2 1 1 pta0 ss1 ? ? pta0/ss1 a1 2 2 iro ? ? ? iro c4 3 ? pta1 kbi1p0 tx1 ? pta1/kbi1p0/tx1 d5 4 ? pta2 kbi1p1 rx1 adp4 pta2/kbi1p1/rx1/adp4 d6 5 ? pta3 kbi1p2 adp5 ? pta3/kbi1p2/adp5 c1 6 3 pta4 ? ? ? pta4 c2 7 4 pta5 ? ? ? pta5 c3 8 5 pta6 ? ? ? pta6 d2 9 6 pta7 ? ? ? pta7 d3 10 7 ptb0 ? ? ? ptb0 d4 11 8 ptb1 blms ? ? ptb1/blms j1 12 9 vssa ? ? ? vssa j2 13 10 vrefl ? ? ? vrefl d1 14 11 nc ? ? ? nc e1 15 12 nc ? ? ? nc f2 16 13 dadp2 ? ? ? dadp2 f1 17 14 nc ? ? ? nc e2 18 15 dadm2 ? ? ? dadm2 f3 19 16 nc ? ? ? nc e3 20 17 nc ? ? ? nc g2 21 18 daco ? ? ? daco g3 22 19 dadp3 ? ? ? dadp3 h4 23 20 nc ? ? ? nc g4 24 21 dadm3 ? ? ? dadm3 g1 25 22 dadp0 ? ? ? dadp0 h1 26 23 dadm0 ? ? ? dadm0 g5 27 24 vrefo ? ? ? vrefo h3 28 ? dadp1 ? ? ? dadp1 h2 29 ? dadm1 ? ? ? dadm1 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 10 j3 30 25 vrefh ? ? ? vrefh j4 31 26 vdda ? ? ? vdda f4 32 27 vss2 ? ? ? vss2 j5 33 28 ptb2 extal1 ? ? ptb2/extal1 j6 34 29 ptb3 xtal1 ? ? ptb3/xtal1 e4 35 30 vdd2 ? ? ? vdd2 j8 36 31 ptb4 extal2 ? ? ptb4/extal2 j9 37 32 ptb5 xtal2 ? ? ptb5/xtal2 g6 38 ? ptb6 kbi1p3 ? ? ptb6/kbi1p3 f7 39 ? ptb7 kbi1p4 ? ? ptb7/kbi1p4 g7 40 33 ptc0 mosi2 ? ? ptc0/mosi2 g8 41 34 ptc1 miso2 ? ? ptc1/miso2 g9 42 35 ptc2 kbi1p5 spsck2 adp6 ptc2/kbi1p5/spsck2/adp6 h5 43 36 ptc3 kbi1p6 ss2 adp7 ptc3/kbi1p6/ss2 /adp7 h6 44 37 ptc4 kbi1p7 cmpp0 adp8 ptc4/kbi1p7/cmpp0/adp8 h8 45 38 ptc5 kbi2p0 cmpp1 adp9 ptc5/kbi2p0/cmpp1/adp9 h9 46 39 ptc6 kbi2p1 pracmpo adp10 ptc6/kbi2p1/pracmpo/adp10 f8 47 40 ptc7 kbi2p2 clkout adp11 ptc7/kbi2p2/clkout/adp11 h7 48 41 ptd0 bkgd ms ? ptd0/bkgd/ms j7 49 42 ptd1 cmpp2 reset ? ptd1/cmpp2/reset e7 50 43 ptd2 tpm1ch0 ? ? ptd2tpm1ch0 e8 51 44 ptd3 tpm1ch1 ? ? ptd3/tpm1ch1 f9 52 45 ptd4 sda tpm1ch2 ? ptd4/sda/tpm1ch2 d7 53 46 ptd5 scl tpm1ch3 ? ptd5/scl/tpm1ch3 e9 54 47 ptd6 tx1 ? ? ptd6/tx1 d8 55 48 ptd7 rx1 ? ? ptd7/rx1 d9 56 ? pte0 kbi2p3 ? ? pte0/kbi2p3 c9 57 ? pte1 kbi2p4 ? ? pte1/kbi2p4 c8 58 ? pte2 kbi2p5 ? ? pte2/kbi2p5 b9 59 ? pte3 kbi2p6 ? ? pte3/kbi2p6 a9 60 49 pte4 cmpp3 tpmclk irq pte4/cmpp3/tpmclk/irq table 3. package pin assignments (continued) package default function alt1 alt2 alt3 composite pin name 81 mapbga 80 lqfp 64 lqfp non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
devices in the mc9s08je128 series freescale semiconductor 11 f5 61 50 vss3 ? ? ? vss3 e5 62 51 vdd3 ? ? ? vdd3 c7 63 52 pte5 tx2 ? ? pte5/tx2 c6 64 53 pte6 rx2 ? ? pte6/rx2 b6 65 ? pte7 tpm2ch3 ? ? pte7/tpm2ch3 b8 66 ? ptf0 tpm2ch2 ? ? ptf0/tpm2ch2 b7 67 54 ptf1 rx2 tpm2ch1 ? ptf1/rx2/tpm2ch1 c5 68 55 ptf2 tx2 tpm2ch0 ? ptf2/tx2/tpm2ch0 a8 69 ? ptf3 scl ? ? ptf3/scl a7 70 ? ptf4 sda ? ? ptf4/sda b5 71 ? ptf5 kbi2p7 ? ? ptf5/kbi2p7 a6 72 56 vusb33 ? ? ? vusb33 b4 73 57 usb_dm ? ? ? usb_dm a4 74 58 usb_dp ? ? ? usb_dp a5 75 59 vbus ? ? ? vbus f6 76 60 vss1 ? ? ? vss1 e6 77 61 vdd1 ? ? ? vdd1 a3 78 62 ptf6 mosi1 ? ? ptf6/mosi1 b1 79 63 ptf7 miso1 ? ? ptf7/miso1 a2 80 64 ptg0 spsck1 ? ? ptg0/spsck1 b3 ? ? ptg1 ? ? ? ptg1 table 3. package pin assignments (continued) package default function alt1 alt2 alt3 composite pin name 81 mapbga 80 lqfp 64 lqfp non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 12 2 preliminary electrical characteristics this section contains electrical specification tables and refere nce timing diagrams for the mc9s 08je128/64 microcontroller, including detailed information on power considerations, dc /ac electrical characteristics, and ac timing specifications. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this ear ly stage of the product life cycle. thes e specifications will, however, be met for production silicon. finalized specifications will be published after complete characterization and device qualifications have been completed. note the parameters specified in this data sheet supersede any values found in the module specifications. 2.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the followin g classification is used and the parameters are tagged accordingly in the tables where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 4. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations. non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 13 2.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in the following table may affect device reliab ility or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advise d that normal precautions be taken to av oid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs ar e tied to an appropriate logic voltage level (f or instance, either v ss or v dd ). table 5. absolute maximum ratings # rating symbol value unit 1 supply voltage v dd ?0.3 to +3.8 v 2 maximum current into v dd i dd 120 ma 3 digital input voltage v in ?0.3 to v dd +0.3 v 4 instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditi ons. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma 5 storage temperature range t stg ?55 to 150 c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 14 2.3 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather th an being controlled by the mcu design. in order to take p i/o into account in power calculations , determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unu sually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 table 6. thermal characteristics # symbol rating value unit 1t a operating temperature range (packaged): c mc9s08je128 ?40 to 105 mc9s08je64 ?40 to 105 2t jmax maximum junction temperature 135 c 3 ja thermal resistance 1,2,3,4 single-layer board ? 1s 1 junction temperature is a function of die size, on-chi p power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow , power dissipation of other components on the board, and board thermal resistance. 2 junction to ambient natural convection 3 1s ? single layer board, one signal layer 4 2s2p ? four layer board, 2 signal and 2 power layers c/w 81-pin mbga 77 80-pin lqfp 55 64-pin lqfp 68 4 ja thermal resistance 1, 2, 3, 4 four-layer board ? 2s2p c/w 81-pin mbga 47 80-pin lqfp 40 64-pin lqfp 49 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 15 solving equation 1 and equation 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 2.4 esd protection characteristics although damage from static discharge is much less common on these devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qualification tests are performe d to ensure that these device s can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with cdf-aec-q00 stress test qualification for automotive grade integrated circuits. ( http://www.aecouncil.com/ ) this device was qualified to aec-q100 rev e. a device is considered to have failed if, after exposure to esd pulses, the devi ce no longer meets the device specification requirements. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. table 7. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulse per pin ? 3 ? machine series resistance r1 0 storage capacitance c 200 pf number of pulse per pin ? 3 ? latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v table 8. esd and latch-up protection characteristics # rating symbol min max unit c 1 human body model (hbm) v hbm 2000 ? v t 2 machine model (mm) v mm 200 ? v t 3 charge device model (cdm) v cdm 500 ? v t 4 latch-up current at t a = 125 ci lat 1 00 ? ma t non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 16 2.5 dc characteristics this section includes information about power supply requirements , i/o pin characteristics, and po wer supply current in various operating modes. table 9. dc characteristics num symbol characteristic condition min typ 1 max unit c 1 v dd operating voltage ?1.8 2 ?3.6v ? 2 v oh output high voltage all i/o pins, low-drive strength 1.8 v, i load = ?600 a v dd ? 0.5 ??v c all i/o pins, high-drive strength 2.7 v, i load = ?10 ma v dd ? 0.5 ??v p 1.8v, i load = ?3 ma v dd ? 0.5 ??v c 3 i oht output high current max total i oh for all ports ???100mad 4 v ol output low voltage all i/o pins, low-drive strength 1.8 v, i load = 600 a ?? 0.5 v c all i/o pins, high-drive strength 2.7 v, i load = 10 ma ?? 0.5 v p 1.8 v, i load = 3 ma ?? 0.5 v c 5 i olt output low current max total i ol for all ports ???100ma d 6v ih input high voltage all digital inputs all digital inputs, v dd > 2.7 v 0.70 x v dd ??v p all digital inputs, 2.7 v > v dd 1.8 v 0.85 x v dd ??v p non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 17 7v il input low voltage all digital inputs all digital inputs, v dd > 2.7 v ? ? 0.35 x v dd v p all digital inputs, 2.7 > v dd 1.8 v ? ? 0.30 x v dd v p 8 v hys input hysteresis all digital inputs ? 0.06 x v dd ??mv c 9 |i in| input leakage current all input only pins (per pin) v in = v dd or v ss ? ? 0.25 (tbd) a p 10 |i oz| hi-z (off-state) leakage current all input/output (per pin) v in = v dd or v ss ??1 (tbd) a p 11 |i oz | leakage current for analog output pins (daco, vrefo) all input/output (per pin) v in = v dd or v ss ?? (tbd) a p 12 |i int | total leakage current 3 f or all pins ? ? 2 ad 13 r pu pull-up resistors ? 17.5 ? 52.5 k p 14 r pd internal pull-down resistors 4 ? 17.5 ? 52.5 k p 15 i ic dc injection current 5, 6, 7 single pin limit v ss > v in > v dd ?0.2 ? 0.2 ma d total mcu limit, includes sum of all stressed pins v ss > v in > v dd ?5 ? 5 ma d 16 c in input capacitance, all pins ? ? ? 8 pf c 17 v ram ram retention voltage ? ? 0.6 1.0 v c 18 v por por re-arm voltage 8 ? 0.9 1.4 1.79 v c 19 t por por re-arm time ? 10 ? ? sd table 9. dc characteristics (continued) num symbol characteristic condition min typ 1 max unit c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 18 20 v lv d h 9 low-voltage detection threshold ? high range v dd falling ? 2.11 2.16 2.22 v p v dd rising ? 2.16 2.23 2.27 v p 21 v lv d l low-voltage detection threshold ? low range 9 v dd falling ? 1.80 1.84 1.88 v p v dd rising ? 1.88 1.93 1.96 v p 22 v lv w h low-voltage warning threshold ? high range 9 v dd falling ? 2.36 2.46 2.56 v p v dd rising ? 2.36 2.46 2.56 v p 23 v lv w l low-voltage warning threshold ? low range 9 v dd falling ? 2.11 2.16 2.22 v p v dd rising ? 2.16 2.23 2.27 v p 24 v hys low-voltage inhibit reset/recover hysteresis 10 ??50?mvc 25 v bg bandgap voltage reference 11 ? 1.15 1.17 1.18 v p 1 typical values are measured at 25 c. characterized, not tested 2 as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above v lvdl . 3 total leakage current is the sum value for all gpio pins ; this leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 na. 4 measured with v in = v dd . 5 all functional non-supply pins are internally clamped to v ss and v dd . 6 input must be current limited to th e value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. table 9. dc characteristics (continued) num symbol characteristic condition min typ 1 max unit c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 19 7 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 8 maximum is highest volta ge that por is guaranteed. 9 run at 1 mhz bus frequency 10 low voltage detection and warning limits measured at 1 mhz bus frequency. 11 factory trimmed at v dd = 3.0 v, temp = 25 c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 20 2.6 supply current characteristics table 10. supply current characteristics # symbol parameter bus freq v dd (v) typ 1 max unit temp (c) c 1 ri dd run supply current fei mode all modules on 24 mhz 3 20 24 ma ?40 to 25 p 24 mhz 3 20 tbd ma 105 p 20 mhz 3 18 ? ma ?40 to 105 t 8 mhz 3 8? ma ?40 to 105 t 1 mhz 3 1.8 ? ma ?40 to 105 t 2 ri dd run supply current fei mode; all modules off 24 mhz 3 12.3 tbd ma ?40 to 105 c 20 mhz 3 10.5 ? ma ?40 to 105 t 8 mhz 3 4.8 ? ma ?40 to 105 t 1 mhz 3 1.3 ? ma ?40 to 105 t 3 ri dd run supply current lps=0; all modules off 16 khz fbilp 3 tbd ? a ?40 to 105 t 16 khz fbelp 3 tbd ? a ?40 to 105 t 4 ri dd run supply current lps=1, all modules off 16 khz fbelp 3 tbd ? a 0 to 70 t 16 khz fbelp 3 tbd ? a ?40 to 105 t non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 21 5 wi dd wait mode supply cur- rent fei mode, all modules off 24 mhz 3 tbd 6 ma ?40 to 105 c 20 mhz 3 tbd ? ma ?40 to 105 t 8 mhz 3 tbd ? ma ?40 to 105 t 1 mhz 3 tbd ? ma ?40 to 105 t 6 s2i dd stop2 mode supply cur- rent n/a 3 0.39 0.6 a ?40 to 25 p n/a 3 tbd tbd a 70 c n/a 3 7 tbd a 85 c n/a 3 16 tbd a 105 p n/a 2 tbd tbd a ?40 to 25 c n/a 2 tbd tbd a 70 c n/a 2 tbd tbd a 85 c n/a 2 tbd tbd a 105 c 7 s3i dd stop3 mode supply cur- rent no clocks active n/a 3 0.55 0.9 a ?40 to 25 p n/a 3 tbd tbd a 70 c n/a 3 14 tbd a 85 c n/a 3 37 tbd a 105 p n/a 2 tbd tbd a ?40 to 25 c n/a 2 tbd tbd a 70 c n/a 2 14 tbd a 85 c n/a 2 tbd tbd a 105 c 1 data in typical column was characterized at 3.0 v, 25c or is typical recommended value. table 10. supply current characteristics (continued) # symbol parameter bus freq v dd (v) typ 1 max unit temp (c) c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 22 2.7 pracmp electricals table 11. typical stop mode adders # parameter condition temperature (c) units c -40257085105 1 lpo ? 50 75 100 150 250 na d 2 erefsten range = hgo = 0 600 (tbd) 650 (tbd) 750 (tbd) 850 (tbd) 1000 (tbd) na d 3irefsten 1 1 not available in stop2 mode. ? 68707786120at 4 tod does not include clock source current 50 75 100 150 250 na d 5lvd 1 lvdse = 1 114 115 123 135 170 a t 6 acmp 1 not using the bandgap (bgbe = 0) 18 20 23 33 65 a t 7 adc 1 adlpc = adlsmp = 1 not using the bandgap (bgbe = 0) 75 85 100 115 165 a t 8 dac 1 high power mode; no load on daco 500 500 500 500 500 a t table 12. pracmp electrical specifications # characteristic symbol min typical max unit c 1 supply voltage v pwr 1.8 ? 3.6 v p 2 supply current (active) (prg enabled) i ddact1 ??60 ac 3 supply current (active) (prg disabled) i ddact2 ??40 ac 4 supply current (acmp and prg all disabled) i dddis ?? 2 nad 5 analog input voltage vain v ss ? 0.3 ? v dd v? 6 analog input offset voltage vaio ? 5 40 mv t 7 analog comparator hysteresis v h 3.0 ? 20.0 mv t 8 analog input leakage current i alkg ?? 1 nad 9 analog comparator initialization delay tainit ? ? 1.0 st non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 23 2.8 12-bit dac electricals 10 programmable reference generator inputs v in2 (v dd25 )1.8 ? 2.75 v ? 11 programmable reference generator setup delay t prgst ?1?sd 12 programmable reference generator step size vstep ?0.25 1 0.25 lsb d 13 programmable reference generator voltage range vprgout v in /32 ? v in vp table 13. dac 12lv operating requirements # characteristic symbo l min max unit c notes 1 supply voltage v dda 1.8 3.6 v p 2 reference voltage v dacr 1.15 3.6 v c 3 temperature t a ?40 105 c c 4 output load capacitance c l ? 100 p f c a small load capacitance (47 pf ) can improve the bandwidth performance of the dac. 5 output load current i l ?1 mac table 12. pracmp electrical specifications # characteristic symbol min typical max unit c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 24 figure 5. offset at half scale vs temperature table 14. dac 12-bit operating behaviors # characteristic symbo l min max unit c notes 1 resolution n 12 12 bit c 2 supply current low-power mode i dda_daclp 50 100 a c 3 supply current high-power mode i dda_dachp 120 500 (tbd) a c 4 f ull-scale settling time (0.5 lsb) (0x080 to 0xf7f or 0xf7f to 0x080) low-power mode ts fs lp ? 200 (tbd) s c 5 f ull-scale settling time (0.5 lsb) (0x080 to 0xf7f or 0xf7f to 0x080) high-power mode ts fs hp ?30 sc 6 code-to-code settling time (0.5 lsb) (0xbf8 to 0xc08 or 0xc08 to 0xbf8) low-power mode ts c-c lp ?5 sc 7 code-to-code settling time (0.5 lsb) (0xbf8 to 0xc08 or 0xc08 to 0xbf8) high-power mode ts c-c hp ?1 (tbd) s c 8 dac output voltage range low (high-power mode, no load, dac set to 0) v dacoutl ? 100 (tbd) mv c 9 dac output voltage range high (high-power mode, no load, dac set to 0x0fff) v dacouth v dacr - 100 ?mvc 10 integral non-linearity error inl ? 8 lsbc 11 differential non-linearity error vdacr is > 2.4 v dnl ? 1 lsbc 12 offset error e o ? 0.5%fsrc 13 gain error e g ? 0.5 (tbd) %fsr c 14 power supply rejection ratio v dd 2.4 v psrr 60 ? db c 15 temperature drift of offset voltage (dac set to 0x0800) t co ? 2 (tbd) mv c see typical drift figure that follows. 16 offset aging coefficient a c ? tbd v/yr c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 25 2.9 adc characteristics table 15. 12-bit adc operating conditions # symb characteristic conditions min typ 1 1 typical values assume v ddad = 3.0 v, temp = 25 c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit c comment 1v ddad supply voltage absolute 1.8 ? 3.6 v d 2 v ddad delta to v dd (v dd -v ddad ) 2 2 dc potential difference. -100 0 +100 mv d 3 v ssad ground voltage delta to v ss (v ss -v ssad ) 2 -100 0 +100 mv d 4v refh ref voltage high 1.13 v ddad v ddad vd 5v refl ref voltage low v ssad v ssad v ssad vd 6v adin input voltage v refl ?v refh vd 7 c adin input capacitance ?45 pf c 8r adin input resistance ? 2 5 k c 9 r as analog source resistance external to mcu assumes adlsmp=0 12-bit mode f adck > 4 mhz ??2 k c f adck < 4 mhz ? ? 5 k c 11/10-bit mode f adck > 8 mhz ??2 k c 4 mhz < f adck < 8 mhz ??5 k c f adck < 4 mhz ? ? 10 k c 9/8-bit mode f adck > 4 mhz ??5 k c f adck < 4 mhz ? ? 10 k c 10 f adck adc conversion clock freq. high speed (adlpc=0, adhsc=1) 1.0 ? 8.0 mhz d high speed (adlpc=0, adhsc=0) 1.0 ? 5.0 mhz d low power (adlpc=1, adhsc=1) 1.0 ? 2.5 mhz d non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 26 figure 6. adc input impedanc e equivalency diagram + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 27 table 16. 12-bit sar adc charac teristics full operating range (v refh = v ddad , > 1.8, v refl = v ssad 8 mhz) characterist ic conditions 1 symb min typ 2 max unit c comment supply current adlpc=1, adhsc=0 i ddad ?215 ? at adlsmp=0 adco=1 adlpc=0, adhsc=0 ? 470 ? adlpc=0, adhsc=1 ? 610 ? supply current stop, reset, module off i ddad ?0.01 ? ac adc asynchronou s clock source adlpc=1, adhsc=0 f adack ?2.4 ? mhz p t adack = 1/f adack adlpc=0, adhsc=0 ? 5.2 ? adlpc=0, adhsc=1 ? 6.2 ? sample time see block guide for sample times conversion time see block guide for conversion times to t a l unadjusted error 12-bit single-ended mode tue ? 1.75 3.5 lsb 3 t32x hardware averaging (avge = %1 avgs = %11) 11-bit differential mode 10-bit single-ended mode ? ? 0.7 0.8 1.5 1.5 t 9-bit differential mode 8-bit single-ended mode ? ? 0.5 0.5 1.0 1.0 t differential non-linearity 12-bit single-ended mode dnl ? 0.7 1lsb 2 t 11-bit differential mode 10-bit single-ended mode ? ? 0.5 0.5 0.75 0.75 t 9-bit differential mode 8-bit single-ended mode ? ? 0.2 0.2 0.5 0.5 t integral non-linearity 12-bit single-ended mode inl ? 1.0 2.5 lsb 2 t 11-bit differential mode 10-bit single-ended mode ? ? 0.5 0.5 1.0 1.0 t 9-bit differential mode 8-bit single-ended mode ? ? 0.3 0.3 0.5 0.5 t non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 28 zero-scale error 12-bit single-ended mode e zs ? 0.7 2.0 lsb 2 tv adin = v ssad 11-bit differential mode 10-bit single-ended mode ? ? 0.4 0.4 1.0 1.0 t 9-bit differential mode 8-bit single-ended mode ? ? 0.2 0.2 0.5 0.5 t full-scale error 12-bit single-ended mode e fs ? 1.0 3.5 lsb 2 tv adin = v ddad 11-bit differential mode 10-bit single-ended mode ? ? 0.4 0.4 1.5 1.5 t 9-bit differential mode 8-bit single-ended mode ? ? 0.2 0.2 0.5 0.5 t quantization error all modes e q ?? 0.5 lsb 2 d input leakage error all modes e il i in * r as mv d i in = leakage current (refer to dc characteristi cs) temp sensor slope ?40 c ? 25c m ? 1.646 ? mv/ c c 25 c ? 125c ? 1.769 ? temp sensor voltage 25 cv temp2 5 ?701.2 ? mv c 1 all accuracy numbers assume the adc is calibrated with v refh =v ddad 2 typical values assume v ddad = 3.0v, temp = 25 c, f adck =2.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3 1 lsb = (v refh - v refl )/2 n table 16. 12-bit sar adc charac teristics full operating range (v refh = v ddad , > 1.8, v refl = v ssad 8 mhz) (continued) characterist ic conditions 1 symb min typ 2 max unit c comment non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 29 2.10 mcg and external oscill ator (xosc) characteristics table 17. mcg (temperature range = ?40 to 105 c ambient) # rating symbol min typical max unit c 1 internal reference startup time t irefst ?55 100 s d 2 average internal reference frequency factory trimmed at vdd=3.0 v and temp=25 c f int_ft ? 31.25 ? khz c user trimmed 31.25 ? 39.0625 c 3 dco output frequency range - trimmed low range (drs=00) f dco_t 16 ? 20 mhz c mid range (drs=01) 32 ? 40 c high range 1 (drs=10) 1 this should not exceed the maximum cpu frequency for this device. 40 ? 60 c 4 resolution of trimmed dco output fre- quency at fixed voltage and tempera- ture with ftrim f dco_res_t ? 0.1 0.2 %f dco c without ftrim ? 0.2 0.4 c 5 total deviation of trimmed dco output frequency over voltage and tempera- ture over voltage and temperature f dco_t ? 1.0 2 %f dco p over fixed voltage and temp range of 0 - 70 c ? 0.5 1 c 6 acquisition time fll 2 2 this specification applies to any time the fll reference source or reference di vider is changed, trim value is changed, dmx32 bit is changed, drs bit is changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is bei ng used as the reference, this specification assumes it is already running. t fll_acquire ?? 1 ms c pll 3 t pll_acquire ?? 1 d 7 long term jitter of dco output clock (averaged over 2ms interval) 4 c jitter ?0.02 0.2 %f dco c 8 vco operating frequency f vco 7.0 ? 55.0 mhz d 9 pll reference frequency range f pll_ref 1.0 ? 2.0 mhz d 10 jitter of pll output clock measured over 625ns 5 long term f pll_jitter_625 ns ? 0.566 4 ? %f pll d 11 lock frequency tolerance entry 6 d lock 1.49 ? 2.98 % d exit 7 d unl 4.47 ? 5.97 d 12 lock time fll t fll_lock ?? t fll_acquire+ 1075(1/ f int_t) s d pll t pll_lock ?? t pll_acquire+ 1075(1/ f pll_re f) d 13 loss of external clock minimum frequency - range = 0 f loc_low (3/5) x f int_t ? ? khz d 14 loss of external clock minimum frequency - range = 1 f loc_high (16/5) x f int_t ? ? khz d non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 30 3 this specification applies to any time the pll vco divide r or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 jitter is the average deviation from the programmed frequ ency measured over the specified interval at maximum f bus . measurements are made with the device powered by filter ed supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 5 625 ns represents 5 time quanta for can applications, under worst-case conditions of 8 mhz can bus clock, 1 mbps can bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. 6 below d lock minimum, the mcg is guaranteed to enter lock. above d lock maximum, the mcg will not enter lock. but if the mcg is already in lock, then the mcg may stay in lock. 7 below d unl minimum, the mcg will not exit lock if already in lock. above d unl maximum, the mcg is guaranteed to exit lock. table 18. xosc (temperature range = ?40 to 105 c ambient) # characteristic symbol min typ 1 max unit 1 oscillator crystal or resonator (erefs = 1, erclken = 1) ? low range (range = 0) f lo 32 ? 38.4 khz ? high range (range = 1), ? fee or fbe mode 2 fhi 1 ? 5 mhz ? high range (range = 1), ? high gain (hgo = 1), ? fbelp mode fhi 1 ? 16 mhz ? high range (range = 1), ? low power (hgo = 0), ? fbelp mode fhi 1 ? 8 mhz 2 load capacitors c 1 c 2 see note 3 3 feedback resistor low range (32 khz to 38.4 khz) r f ? 10 ? m high range (1 mhz to 16 mhz) ?? 1 ? 4 series resistor ? low range low gain (hgo = 0) r s ?0 ? k high gain (hgo = 1) ? 100 ? 5 series resistor ? high range ? low gain (hgo = 0) k ? high gain (hgo = 1) 8 mhz r s ?0 0 4 mhz ? 0 10 1 mhz ? 0 20 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 31 o 6 crystal start-up time 4, 5 low range, low gain (range = 0, hgo = 0) t cstl ? 200 ? ms low range, high gain (range = 0, hgo = 1) ? 400 ? high range, low gain (range = 1, hgo = 0) t csth ?5 ? high range, high gain (range = 1, hgo = 1) ?15 ? 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. 2 when mcg is configured for fee or fbe mode, input clock sour ce must be divisible using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 see crystal or resonator ma nufacturer?s recommendation. 4 this parameter is characterized and not tested on each device. 5 proper pc board layout procedures must be followed to achieve specifications. table 18. xosc (temperature range = ?40 to 105 c ambient) # characteristic symbol min typ 1 max unit non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 32 2.11 ac characteristics this section describes ac timing charact eristics for each pe ripheral system. 2.11.1 control timing table 19. control timing # symbol parameter min typical 1 max c unit 1 f bus bus frequency (t cyc = 1/f bus )m h z v dd 1.8 v dc ? 10 d v dd > 2.1 v dc ? 20 d v dd > 2.4 v dc ? 24 d 2 t lpo internal low-power oscillator period 800 990 (tbd) 1500 d s 3 t extrst external reset pulse width 2 (t cyc = 1/f self_reset ) 100 ? ? d ns 4t rstdrv reset low drive 66 x t cyc ??dns 5 t mssu active background debug mode latch setup time 500 ? ? d ns 6 t msh active background debug mode latch hold time 100 ? ? d ns 7t ilih, t ihil irq pulse width ? asynchronous path 2 ? synchronous path 3 100 1.5 x t cyc ?? d ns 8t ilih, t ihil kbipx pulse width ? asynchronous path 2 ? synchronous path 3 100 1.5 x t cyc ?? d ns non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 33 figure 7. reset timing figure 8. irq/kbipx timing 9t rise , t fall port rise and fall time (load = 50 pf) 4 , low drive ns slew rate control disabled (ptxse = 0) ?11?d slew rate control enabled (ptxse = 1) ?35?d slew rate control disabled (ptxse = 0) ?40?d slew rate control enabled (ptxse = 1) ?75?d 1 typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. 2 this is the shortest pulse that is guaranteed to be reco gnized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. 3 this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is by passed so shorter pulses can be recognized in that case. 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 105 c. table 19. control timing # symbol parameter min typical 1 max c unit t extrst reset pin t ihil irq/kbipx t ilih irq/kbipx non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 34 2.11.2 tpm timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. figure 9. timer external clock figure 10. timer input capture pulse table 20. tpm input timing # c function symbol min max unit 1 ? external clock frequency f tpmext dc f bus /4 mhz 2 ? external clock period t tpmext 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t tpmext t clkh t clkl tpmxclk t icpw tpmxchn t icpw tpmxchn non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 35 2.12 spi characteristics table 21 and figure 11 through figure 14 describe the timing requirements for the spi system. table 21. spi timing no. 1 1 numbers in this column identify elements in figure 11 through figure 14 . characteristic 2 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min max unit c 1 operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz hz d 2 spsck period master slave t spsck 2 4 2048 ? t cyc t cyc d 3 enable lead time master slave t lead 1 / 2 1 ? ? t spsck t cyc d 4 enable lag time master slave t lag 1 / 2 1 ? ? t spsck t cyc d 5 clock (spsck) high or low time master slave t wspsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns ns d 6 data setup time (inputs) master slave t su t su 15 15 ? ? ns ns d 7 data hold time (inputs) master slave t hi t hi 0 25 ? ? ns ns d 8 slave access time 3 3 time to data active from high-impedance state. t a ?1t cyc d 9 slave miso disable time 4 4 hold time to high-impedance state. t dis ?1t cyc d 10 data valid (after spsck edge) master slave t v ? ? 25 25 ns ns d 11 data hold time (outputs) master slave t ho 0 0 ? ? ns ns d 12 rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns d 13 fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns d non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 36 figure 11. spi master timing (cpha = 0) figure 12. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 2 2 3 5 6 7 11 12 5 11 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit orde r is lsb, bit 1, ..., bit 6, msb. notes: 2 2 3 4 5 6 7 11 12 5 4 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 37 figure 13. spi slave timing (cpha = 0) figure 14. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined, but normally ms b of character just received 2 2 3 4 6 7 8 9 11 12 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined, but normally ls b of character just received 2 2 3 4 6 7 8 9 11 12 4 5 5 non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 38 2.13 flash specifications this section provides details about program/erase ti mes and program-erase endurance for the flash memory. program and erase operations do not require any special power sources ot her than the normal v dd supply. for more detailed information about program/erase oper ations, see the memory chapter in the reference manual for this device (mc9s08je128rm). table 22. flash characteristics # characteristic symbol min typical max unit c 1 supply voltage for program/erase -40 c to 105 cv prog/erase 1.8 ? 3.6 v d 2 supply voltage for read operation v read 1.8 ? 3.6 v d 3 internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 ? 200 khz d 4 internal fclk period (1/fclk) t fcyc 5 ? 6.67 sd 5 byte program time (random location) 2 t prog 9t fcyc p 6 byte program time (burst mode) 2 t burst 4t fcyc p 7 page erase time 2 2 these values are hardware state machine controlled. user co de does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc p 8 mass erase time 2 t mass 20,000 t fcyc p 9 program/erase endurance 3 t l to t h = ?40 c to + 105c t = 25 c 3 typical endurance for flash was evaluated for this product family on the hc9s12dx64. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles c 10 data retention 4 4 typical data retention values are based on intrinsic capability of the te chnology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. t d_ret 15 100 ? years c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrica l characteristics freescale semiconductor 39 2.14 usb electricals the usb electricals for the usb on-the-g o module conform to the standards documented by the universal serial bus implementers forum. for the mo st up-to-date standards, visit http://www.usb.org. if the freescale usb on-the-go implementa tion has electrical ch aracteristics that deviate fr om the standard or require additional information, this space would be used to communicate that information. table 23. internal usb 3.3 v voltage regulator characteristics # characteristic symbol min typ max unit c 1 regulator operating voltage v regin 3.9 ? 5.5 v c 2 vreg output v regout 33.33.6vp 3 v usb33 input with internal vreg disabled v usb33in 33.33.6vc 4 vreg quiescent current i vrq ?0.5?mac non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
preliminary electrical characteristics freescale semiconductor 40 2.15 vref electrical specifications table 24. vref electrical specifications num characteristic symbol min max unit c 1 supply voltage v dda 1.80 3.6 v c 2 temperature t a ?40 105 c c 3 output load capacitance c l ? 100 nf d 4 maximum load ? ? 10 ma ? 5 voltage reference output with factory tr i m . v dd = 3 v. vout 1.140 1.160 v p 6 temperature drift (vmin - vmax across the full temperature range) tdrift ? 10 (tbd) mv 1 1 see typical chart below. t 7 aging coefficient ac ? tbd ppm/year c 8 powered down current (off mode, vrefen=0, vrsten=0) i ? 0.10 a c 9 bandgap only (mode_lv[1:0] = 00) i ? 75 a t 10 low-power buffer (mode_lv[1:0] = 01) i ? 125 a t 11 tight-regulation buffer (mode_lv[1:0] = 10) i?1 . 1m at 12 load regulation mode_lv = 10 ? ? 100 v/ma c 13 line regulation (power supply rejection) dc ? tbd mv c 14 ac tbd ?d b table 25. vref limited range operating requirements # characteristic symbol min max unit c notes 1 temperature t a 05 0 cc table 26. vref limited range operating behaviors # characteristic symbol min max unit c notes 1 voltage reference output with factory trim vout tbd tbd a c non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
ordering information freescale semiconductor 41 figure 15. typical output vs. temperature figure 16. typical output vs. v dd 3 ordering information this appendix contains ordering information for the de vice numbering system. mc9s08je128 and mc9s08je64 devices. tbd non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
ordering information freescale semiconductor 42 3.1 device numbering system example of the device numbering system: 3.2 package information 3.3 mechanical drawings table 28 provides the available package types and their document numbers. the latest package outline/mechani cal drawings are available on the mc9s08je128 series product summary pages at http://www.freescale.com . to view the latest drawing, either: ? click on the appropriate link in table 28, or ? open a browser to the freescale ? website ( http://www.freescale.com ), and enter the appropriate document number (from table 28 ) in the ?enter keyword? search box at the top of the page. table 27. device numbering system device number 1 1 see ta b l e 2 for a complete description of modules included on each device. memory available packages 2 2 see table 28 for package information. flash ram mc9s08je128 131,072 12,288 64 lqfp 131,072 12,288 80 lqfp 131,072 12,288 81 mapbga mc9s08je64 65,536 12,288 64 lqfp table 28. package descriptions pin count package type abbreviation designator case no. document no. 64 low quad flat package lqfp lh 840f-02 98ass23234w 80 low quad flat package lqfp lk 917-01 98ass23174w 81 mapbga package map pbga mb 1662-01 98asa10670d mc temperature range family memory status core (v = ?40 c to 105 c) (9 = flash-based) 9 s08 (mc = fully qualified) package designator (see table 28 ) approximate flash size in kbytes je 128 v xx (c = ?40 c to 85 c) non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
revision history freescale semiconductor 43 4 revision history to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. rev date description of changes 06/2009 initial release of the data sheet. 17/2009 updated mcg and xosc average internal reference frequency . 2 04/2010 updated electrical characteristic data. non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages
document number: mc9s08je128 rev. 3 04/2010 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center http://compass.freescale.net/go/168063291 1-800-441-2447 or 1-303-675-2140 fax: 1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009-2010. all rights reserved. non-disclosure agreement required preliminary ? subject to change because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mc9s08je128 products in 81 mapbga packages

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